Integrated Circuit
An integrated circuit (also known as IC, microcircuit, microchip, silicon chip, or chip) is a miniaturized electronic circuit that is manufactured in the surface of a thin substrate of semiconductor material. The electronic circuit may contain active devices, such as transistors that provide electrical gain, and passive devices, such as resistors, capacitors, and diodes.
Field-Effect Transistor
One type of transistor, known as a field-effect transistor (FET), relies on an electric field provided by a gate contact to control the shape and hence the conductivity of a channel in the semiconductor material between a source contact and a drain contact.
A metal-oxide-semiconductor field-effect transistor (MOSFET) is a common field-effect transistor in both digital and analog circuits. The metal-oxide-semiconductor phrase references the physical structure of early and the latest field-effect transistors, wherein a metal gate electrode is placed on top of an oxide insulator, which in turn is placed on top of a semiconductor material. The MOSFET has a channel of n-type or p-type semiconductor material, and is accordingly called a nMOSFET or a pMOSFET.
A primary characteristic for the gate material of a MOSFET is that it is a good conductor. Examples of gate materials include highly-doped polycrystalline silicon (“polysilicon”), metal (e.g., tantalum, tungsten, tantalum nitride, and titanium nitride), and a blended material of polysilicon and metal called silicide, each having associated advantages and disadvantages. Polysilicon gates are not metal have been used for the past twenty years. Therefore, the term ‘metal’ in the phrase “MOSFET” is often incorrect as process technologies may vary. Metal gates were used for early MOSFETs and are again now being used for fabricating semiconductors at 65 nm and smaller processes.
FIG. 1 illustrates schematic diagrams of an nMOSFET and a pMOSFET. Three reliability issues associated with MOSFETS include time dependent dielectric breakdown (TDDB), hot carrier injection (HCI), and bias temperature instability (BTI).
TDDB occurs when a MOSFET's gate to terminal voltage (either Vgs or Vgd) exceeds a limit permitted by the manufacturing process causing the gate-oxide to deteriorate with time and eventually break down.
HCI occurs in semiconductors when either an electron or a “hole” gains sufficient kinetic energy to overcome a potential barrier, becoming a “hot carrier” and then migrates to a different area of the device. HCI usually occurs when a MOSFET is turned on and its drain-source voltage (Vds) exceeds a limit permitted by the manufacturing process causing an electrical charge in the drain-source channel to have enough energy to be injected into the gate dielectric, thereby causing the threshold voltage to shift and may eventually damage the gate.
Negative BTI (NBTI) only affects pMOSFETs, and positive BTI (PBTI) only affects nMOSFETs. A positive charge builds up at the channel interface of pMOSFETs under negative bias and high temperature conditions (positive bias for nMOSFETs). This increases a threshold voltage and decreases IDsat over time causing device instability and performance degradation.
Although designing longer channel lengths can minimize the HCI effect, the semiconductor manufacturing process controls the TDDB and NBTI effects, and design guidelines must be followed to ensure device reliability.
Perhaps the most stressed condition for MOSFETs happens when powering down the MOSFETs. In a power down mode, the gate terminal may be connected to ground for nMOSFETs or to a positive power supply voltage for pMOSFETs, while the other terminals (e.g., drain or source) may be forced in other directions to undesirable voltage levels. This condition is especially true when a circuit uses a power supply voltage above the semiconductor process limit.
Analog and Digital Circuits
An integrated circuit may contain analog and/or digital electronic circuits, and may combine analog and digital MOSFET circuitry on the same semiconductor for higher integration. Combined analog and digital MOSFET circuitry may be referred to as a “system on a chip” (SOC), and has found wide applications in wireless communications, mobile computing, computers, and consumer electronics. Analog electronic circuits use an analog signals that are continuously variable signals. Digital electronic circuits use digital signals that have either low or high voltage levels, representing a logic “0” and a logic “1,” respectively.
The growth of digital circuits like the microprocessor has provided the motivation to advance MOSFET technology faster than any other type of silicon-based transistor.
A principal reason for the success of the MOSFET was the development of digital complementary metal-oxide-semiconductor (CMOS) logic, which uses p- and n-channel MOSFETs as building blocks. CMOS logic is continuously being scaled down to achieve low-cost, high density, low power, and high-speed digital systems. In CMOS logic, a collection of nMOSFETs is arranged in a pull-down network between the output and the lower-voltage power supply rail (often named Vss or quite often ground). Instead of the load resistor of nMOS logic gates, CMOS logic gates have a collection of nMOSFETs in a pull-up network between the output and the higher-voltage rail (often named Vdd). Now pull-up and pull-down refer to the idea that the output node, which happens to be where the pull-up and pull-down networks intersect, exhibit some internal capacitance that is charged or discharged respectively through pathways formed by the p/nMOS networks for various inputs. This capacitance is charged when there is a direct path from Vdd to the output, and discharged when there is a direct path from output to ground. A digital CMOS circuit ideally may not be in a pull-up and pull-down phase at the same time, or else both the p/n-networks will fight to keep the voltage on the capacitance either Vdd or ground. The p-type transistor network is complementary to the n-type transistor network, so that when the n-type is off, the p-type is on, and vice-versa.
MOSFETs are widely used for analog circuits as well. Some of the advantages of MOSFETs are that due to their positive temperature coefficient, they do not suffer as much from thermal runaway as bipolar junction transistors (BJTs) do and that their linear region allows them to be used as precision resistors, which can have a much higher controlled resistance than BJTs. They also can be formed into capacitors and specialized circuits that allow op-amps made from them to appear as inductors, thereby permitting all of the normal analog devices, except for diodes (which can be made smaller than a MOSFET anyway), to be built entirely out of MOSFETs. This allows for complete analog circuits to be made on a silicon chip in a much smaller space.
Engineering Tradeoffs
Although digital circuits can directly benefit from scaling down the size of the devices, it is not always true for analog circuits. When the sizes of the devices are scaled down for a digital circuit, the digital circuit's power supply voltage is also lowered to reduce power supply requirements and to insure reliability of the devices. However, lowering the power supply voltage for an analog circuit limits the dynamic range of the analog circuit, which reduces the performance of the analog circuit. Raising the power supply voltage for an analog circuit improves the dynamic range of the analog circuit to maintain the performance of the analog circuit, but causes the analog circuit to consume more power, and may threaten the reliability of analog circuit, especially in the power down mode.
Prior Solutions
One solution to overcome the disadvantages of scaling down the size of devices in an analog circuit in a SOC is to manufacture an integrated circuit using a dual-gate oxide process for devices in the digital and analog circuits. In a dual-gate oxide process, the digital circuit uses thin-gate oxide devices to permit a lower power supply voltage to be used, and the analog circuit uses thick-gate oxide devices to permit a higher power supply voltage to be used and to provide higher reliability devices. A disadvantage of this solution is that manufacturing an integrated circuit with a dual-gate oxide process costs more than manufacturing one with a single-oxide gate process because additional masks, processing steps, and time are needed to manufacture the thick-gate oxide for the analog devices. Alternatively, if the thick-gate oxide process were applied to the digital and analog circuits, then a single thick-gate oxide process would be used for the entire integrated circuit at a cost to the integrated circuit of the thick-gate oxide process over the thin-gate process. In both cases, the extra cost may be not acceptable in low cost SOC designs, especially in the case when a majority of the circuits in a SOC are digital and a minority of the circuits are analog.
Another solution to overcome the disadvantages of scaling down the size of devices in an analog circuit in a SOC is to use a power down circuit with a single power supply voltage (VddH), as shown in FIG. 2. The analog circuit, represented as a conventional operational transconductance amplifier (OTA) 102, for example, and the digital circuit, represented as an inverter 202, for example, both use the same single power supply voltage (VddH), as shown in FIG. 2. The single power supply voltage (VddH) operates within the reliability requirements of the OTA 201 and the inverter 202.
The analog circuit, represented as the OTA 201 shown in FIG. 2, as well as FIGS. 3, 4, and 6 is conventional. The OTA 201 includes pMOSFETs, MP1-9, and nMOSFETs, MN1-10. Source terminals of MP2, 4, 6, and 7 are electrically coupled to a high voltage potential, VddH (e.g., 2.1V minimum, 2.2V nominal, 2.3V maximum). Source terminals of MN2, 3, 4, and 5 are electrically coupled to a ground voltage potential, Vss (e.g., 0V). The inputs terminals for the OTA 201 are the gate terminals of MN6 and MN7 illustrated as “in” and “ip,” respectively. The output terminals for the OTA 201 are the drain terminals of MN8 and MN9 illustrated as “on” and “op,” respectively. The bias terminal for the OTA 201 is the drain terminal of MN1, which is also electrically coupled to the gate terminal of MN1.
The digital circuit, represented as the inverter 202 shown in FIG. 2, as well as in FIGS. 3, 4, and 6, is also conventional. The inverter 202 is adapted to receive a power down signal, PD, and adapted to invert the power down signal, PD, to an inverted power down signal, PDN. When the PD signal is logic 1 or a high voltage, such as a high voltage potential, VddH, the inverted power down signal, PDN, is logic 0 or a low voltage, such as a ground potential, Vss. When the PD signal is logic 0, or a low voltage, such as a ground potential, Vss, the inverted power down signal, PDN, is logic 1 or a high voltage, such as a high voltage potential, VddH.
The OTA 201 powers down when the inverter 202 receives the power down signal, PD, as logic 1 or a high voltage. The OTA 201 does not power down and operates in a normal state when the inverter 202 receives the power down signal, PD, as logic 0 or a low voltage.
To power down the OTA 201, the power down signal, PD, representing logic 1 or a high voltage, is provided to the inverter 202 to generate the inverted power down signal, PDN, representing logic 0 or a low voltage. The power down signal, PD, representing logic 1 or a high voltage, is applied to the gate terminal of MN11. The inverted power down signal, PDN, representing logic 0 or a low voltage, is applied to the gate terminal of MP10 and MP11. After power down, no current flows between the high voltage supply, VddH, and the ground voltage, Vss.
A logic 0 or a low voltage applied to the gate terminal of MP10 removes a logic 1 or high voltage, VddH, from the drain terminal of MP10, as well as the gate terminals of MP1, MP3, MP5, MP8, and MP9, to turn off MP1, MP3, MP5, MP8, and MP9, respectively. A logic 0 or a low voltage applied to the gate terminal of MP11 removes a logic 1 or high voltage, VddH, from the drain terminal of MP11, as well as the gate terminals of MP2, MP4, MP6, and MP7, to turn off MP2, MP4, MP6, and MP7, respectively. A logic 1 or high voltage, VddH, applied to the gate terminal of MP11 provides a logic 0 or low voltage, Vss, at the drain terminal of MP11, as well as the gate terminals of MN2, MN3, MN4, and MN5, to turn off MN2, MN3, MN4, and MN5, respectively.
One disadvantage of the integrated circuit, shown in FIG. 2, is the additional associated with the dual-gate oxide and single-gate oxide processes, while maintaining reliability and dynamic range for the analog circuit, as explained above.
Yet another solution to overcome the disadvantages of scaling down the size of devices in an analog circuit in a SOC is to use the same power down circuit, as shown in FIG. 2, with a dual power supply design (VddH and VddL), as shown in FIG. 3. A low voltage supply, VddL (e.g., 1.2V minimum, 1.25V nominal, 1.3V maximum), represents the lowest voltage that may be used with the thin-gate oxide process while maintaining acceptable device reliability. FIG. 3 assumes that the a single thin-gate oxide process is used for both the digital and analog circuits to reduce cost, and the high voltage supply, VddH, is used to maintain an acceptable dynamic range for the analog circuit at the risk of exceeding the device reliability limits.
The integrated circuit, shown in FIG. 3, has several disadvantages. First, the gate terminals of MP10 and MP11 may not be pulled low to ground in the normal operation mode, as permitted in FIG. 2, because their Vgs voltage will be as high as VddH, which exceeds the low voltage supply, VddL, limit of the thin-gate oxide process. Second, in the power down mode, nodes A and B are forced to the high voltage supply, VddH, and node D is forced to the ground potential, Vss, by MN11, which causes reliability problems across the gate-drain terminals, Vgs, of MN2 and MN3. Third, when both the top (MP2-9) and bottom (MN1-5) bias devices are turned off, node C and the OTA 201 outputs “op” and “on” are floating and may be stuck at a voltage close to the high voltage supply, VddH, which causes reliability problems for MN8-10, and any other circuit connected to the outputs “op” and “on.” For these reasons, the traditional power down scheme, shown in FIG. 2, may not be used in the dual power supply design, shown in FIG. 3.
Still another solution to overcome the disadvantages of scaling down the size of devices in an analog circuit in a integrated circuit is to use a power down circuit with a dual power supply design and a voltage shifter 203, as shown in FIG. 4. To solve the reliability issues related to MP10 and MP11 in the power down mode, a voltage level shifter 203 shifts the inverted powder down signal, PDN, to a higher voltage level instead of the ground potential, Vss. To meet the reliability requirement, the low level voltage of the inverted power down signal, PDN, is shifted to a voltage level of VddH-VddL (e.g., 2.2V−1.25V=0.95V) so the gate-source voltage for MP10 and MP1 in the power down mode is the low voltage, VddL, which is within the reliability limit of the semiconductor manufacturing process. During the normal operation mode, the inverted power down signal, PDN, should be the low voltage, VddL. Therefore, in FIG. 4, the voltage level shifter 203 is needed to shift a voltage of the inverted power down signal, PDN, from Vss (LOW)/NVddL(HIGH) to VddL(LOW)/VddH(HIGH), which is not trivial to design, and may need its own power down control circuit. The power down devices MN11-MN15 are connected in series with the nMOS bias devices, MN1, MN2, MN 4, MN 6, and MN 7, respectively. The power down devices MP10˜MP14 are connected in series with the pMOS bias devices, MP1-5, respectively. In FIG. 4, in the power down mode, nodes A and B will not be forced to VddH, shown in FIG. 3.
The integrated circuit, shown in FIG. 4, has several disadvantages. First, the voltage level shifter 203 is needed to generate the inverted power down signal, PDN, which consumes power and is not trivial to design, especially in the conditions when VddH is below 2 VddL. Second, nodes A, B, C, D, E, F, “on,” “op,” and other internal nodes are floating in the power down mode, which may cause reliability problems. The reason behind this is that while MN11-15 devices are shut down immediately after the power down signal, PD, goes low. The top pMOS power down signal is always delayed relative to the bottom nMOS power down signal, because PDN and PDN_H have to go through the inverter 202 and the level shifter 203, rather than just the inverter 202. Therefore, after the bottom nMOS devices, MN1-15, are turned off, but before the top power down signal is triggered, all the internal node voltages are forced to VddH, which may cause reliability problems to the bottom NMOS devices, MN2-5. Even if the top and bottom power down signals match perfectly in time (i.e., triggered at the exact time), which is not trivial to implement because the internal nodes are floating, the internal nodes may still drift to either ground or VddH because of the leakage current mismatches between nMOS path and pMOS path.
Accordingly, there is a need for a method and apparatus for powering down an analog circuit in system on a chip having dual power supply voltages (e.g., VddH and VddL) and manufactured using a single thin-gate oxide process. Further, the method and apparatus should not use a voltage level shifter and should not have floating voltages at the internal analog circuit nodes. Further, the method and apparatus should operate within device reliability limits and be designed and manufactured with minimal cost.